1. Technical Field
The present invention relates generally to a memory apparatus, and more particularly, to a semiconductor apparatus for improving the reliability of a nonvolatile memory apparatus and a method for fabricating the same.
2. Related Art
In general, a cell array in a nonvolatile memory apparatus includes a plurality of strings, and each string is made of memory cells connected in series with transistors formed at the string ends. The memory cells from different strings are electrically connected through word lines. Each string is electrically connected to a page buffer that senses data through a bit line.
A nonvolatile memory apparatus is electrically erasable and programmable. In an erase operation, a low gate voltage is applied to a control gate to extract electrons that were injected into a floating gate by the F-N tunneling effect,.
FIG. 1 illustrates a conventional erase operation in a nonvolatile memory apparatus.
Referring to FIG. 1, an erase operation is performed by floating a source select line and a drain select line, then applying a ground voltage (e.g., 0V) to a word line included in a block unit, and then applying a high voltage to a well formed in a semiconductor substrate. The threshold voltages of the cells to be erased through the above erase operation are distributed in an EV1 state as illustrated in FIG. 1.
However, some memory cells may be erased more excessively than other cells due to certain operating characteristics of the memory cells. The threshold voltages of the cells to be erased have to be distributed according to an erase voltage level EVL, but the threshold voltage distribution of the cells that were erased more excessively becomes lower than the erase voltage level EVL as illustrated in FIG. 1.
A Soft program On Chip (SOC) operation is performed to correct the threshold voltage distribution of the excessively-erased cells. The SOC operation repeats a program operation and a verify operation to correct a threshold voltage distribution of an EV1 state to a threshold voltage distribution of an EV2 state, that is, about the erase voltage level EVL.
The SOC operation can adjust the threshold voltage distribution of erased cells to about the erase voltage level EVL. However, the SOC operation fails to reduce the width of the threshold voltage distribution of the erased cells.
When the width of the threshold voltage distribution of erased cells is not sufficiently narrow, it will increase the program operation time. A wider width of the threshold voltage distribution of erased cells will also increase the threshold voltage distribution of programmed cells and cause an interference, thus degrading the reliability of the nonvolatile memory apparatus.